Modern integrated circuits use conductive interconnects to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular interconnect materials include copper, aluminum, copper alloys, and aluminum alloys. In order to accommodate desired interconnect densities, multiple layers of interconnects, referred to as “metallization layers” may be used.
A typical method of forming an interconnect, particularly a copper interconnect, is a damascene process. A common conventional damascene process usually involves the following, as illustrated by FIGS. 1(a)–1(c):    (1) Deposit an etch stop 120 on a substrate 110.    (2) Deposit a dielectric layer 130. Because dielectric layer 130 will ultimately fill the space between interconnects within a particular layer, it may be referred to as an interlayer dielectric or ILD.    (3) Form a trench 132 having via openings 134 in the dielectric layer 130 and etch stop 120 to an underlying layer, such as substrate 110. For example, via openings 134 may expose the source, drain, or gate of a transistor. A hard mask 140 may be used to form the trench, but is not necessary. Structure 11 shows a partially fabricated interconnect layer after operation 3.    (4) Line the trench 132 and via opening 134 with a barrier layer of a refractory material, for example titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The barrier layer serves to inhibit the diffusion of the interconnect material that will subsequently be introduced in the via and trench into the interlayer dielectric.    (5) Deposit a suitable seed material on the wall or walls of trench 132 and via opening 134. Suitable seed materials for the deposition of copper interconnect material include copper (Cu), nickel (Ni), and cobalt (Co).    (6) Deposit an interconnect material 150, such as copper, into the trench and via openings. Deposition methods include electroplating and physical deposition. Structure 12 shows a partially fabricated interconnect layer after operation 6.    (7) Planarize to remove any excess interconnect material and to form interconnect 160. Structure 13 shows an interconnect layer after operation 7.
Operations 1 through 7 may be repeated multiple times to fabricate multiple layers of metallization. After the final layer of metallization is fabricated, a dielectric material may be deposited to isolate the structure.
Although many different materials have been used as interconnect materials, copper has become a popular choice for various reasons. For example, copper has a low resistivity and a high melting point compared to aluminum or aluminum alloys. Low resistivity enables the use of thinner interconnects without sacrificing conductivity, and high melting point decreases susceptibility to migration during operation, which can lead to undesirable voids in the interconnect.
As chip processing technology advances and the packing density of devices increases, it is desirable to similarly increase the density of interconnects. This may be achieved by reducing the interconnect metal pitch, and by increasing the number of metallization levels. However, reduced interconnect pitch and/or increased metallization levels may lead to problems such as increased capacitance and degraded RC delay, cross-talk noise, and voids in the interconnect due to electro migration or stress migration.
What is needed are improved interconnect structures and techniques for improving the fabrication and properties of an interconnect structure.